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Toshiba Develops Next-generation Gate Driver Technology that Reduces Noise and Losses in SiC Devices

-Realizing smaller, lower-cost, and lower-power-consumption electrical power systems for electric vehicles and data centers in the field of power semiconductors-

17 Feb, 2026
Toshiba Corporation

Overview

Kawasaki - Toshiba has developed two next-generation gate driver technologies that maximize the performance of silicon carbide (SiC) devices, next-generation devices in the field of power semiconductors— an area that is a core strength of the Toshiba Group. These technologies increase efficiency, reduce size, and improve the reliability of SiC devices, enhancing energy efficiency in applications such as electric vehicles (EVs) and enhancing higher current density in power systems for data centers, including uninterruptible power supplies (UPS), ultimately contributing to the realization of a decarbonized society.
Power semiconductors efficiently control and operate power electronics through repeatedly turning the power ON and OFF (switching). Unlike the silicon (Si) devices, which are currently the most widespread, SiC devices have a tradeoff relationship between offering superior high-speed switching and greatly reduced power loss during transitions from ON to OFF and from OFF to ON, as well as a reduction in efficiency resulting from noise occurring due to the high-speed operation (high frequency). To realize high-performance SiC devices, it is essential to not only optimize this tradeoff but also handle the increase in loss that occurs in the drive IC accompanying the higher frequency and increased capacity of the power semiconductor power module.
Toshiba has developed “feedback-type active gate driver technology” that enables controlling the optimal balance between loss and noise through the world’s first automatic drive waveform generator function, and “low-loss gate driver technology” (binary weighted switched-capacitor) that realizes for the first time a multi-level gate voltage generator using a small number of capacitors and greatly reduces drive loss. This reduces the power loss of SiC devices while simultaneously realizing higher efficiency, smaller size, and improved reliability.
Toshiba will present the details of these technologies at the 2026 IEEE International Solid-State Circuits Conference—the largest international conference in the field of semiconductors—to be held in San Francisco from February 15 to 19, 2026.

Development background

In recent years, it has been necessary to reduce the size and increase the efficiency of power electronics devices, which are used in EVs and data center power supplies, in order to realize higher frequencies and higher switching speeds. Although SiC devices have attracted attention because of their excellent high-speed switching and expected large decrease in power losses compared with conventional Si devices(*1), they have a trade-off between decreasing the energy loss during driving and increased noise. In previous technologies aimed at ameliorating this trade-off(*2), stable operation and increased efficiency were difficult to achieve due to environmental variations as well as variations in device properties. Furthermore, the power consumed and the heat generated by the driver for driving large devices and increasing the efficiency and reducing the size of the driver have also been key challenges. Toshiba has developed two innovative technologies to address these challenges.

Figure : Effects and technical challenges in applying SiC to power electronics devices

Features of the technology

The two new technologies are both related to gate driver ICs, which provide the signal that drives SiC devices.

1. Feedback-type Active Gate Driver

Generates the optimal drive waveform in real time depending on temperature and load variations. A prototype circuit achieved a maximum of 28% loss reduction and 58% surge suppression.

This is a technology for getting the most out of the high-efficiency and high-speed switching characteristics of SiC power devices and suppressing the generation of noise. Sudden variations in voltage and surges are suppressed by generating the optimal waveform in a gate driver fitted with a unique feedback function. Although the power device voltage needs to be detected to perform feedback, given that this detected voltage includes error in conventional methods, the correct waveform cannot be generated. Therefore, the proposed technology makes it possible to detect the operating voltage accurately by equipping a circuit to correct the error. This generates the optimal drive waveform in real time, making it possible to continually optimize the voltage surges and transition rates that cause noise. In a prototype circuit, the proposed technology realized stable operation under environmental variations such as temperature and load variations, achieving a maximum switching loss reduction of 28% and maximum surge suppression of 58%. This technology will make a large contribution to reducing the size and increasing the efficiency of power electronics devices that handle high voltages and large currents, including inverters for EVs.

Figure 1: Detection error–correction circuit
Figure 2: Developed feedback-type active gate driver and effect on improving characteristics

2. Low-loss Gate Driver

Generates nine levels of gate voltages while reducing the number of capacitors by using a unique binary weighting method. Realizes a drive loss reduction of 84% in a prototype circuit.

In conventional gate drivers, the device becomes larger as the operating frequency and current of the power device increase, and drive loss also increases in proportion to this. For this reason, it has become an obstacle to realizing increased power efficiency and smaller size. A method called “switched-capacitor circuit” has been used to reduce gate voltage in steps using a circuit configuration as a method for reducing drive loss. However, as the number of levels increases, the number of capacitors needed also increases, which in turn increases the number of components, making it difficult to reduce size. Toshiba has developed a method that can reduce the number of capacitors needed compared with the conventional method by employing binary weighting of the capacitances and tolerable voltages of the capacitors and using a unique switching-connection configuration. The prototype circuit generated nine levels of stepped gate voltages using a mere four capacitors, and achieved a drive loss reduction of 84%. This technology will contribute to increased efficiency, particularly during light loads, and reducing the size of the overall system.

Figure 3: Structure of the proposed circuit and drive loss-reduction effect of the stepped drive
Figure 4: Developed low-loss gate driver and characteristics-improvement effect

Future developments

Toshiba is working on further research and development of this technology, with the aim of achieving early adoption at Toshiba Electronic Devices & Storage Corporation. Toshiba will contribute to the realization of carbon neutrality through higher performance of various power electronics devices.