Corporate Research & Development Center

Development of an SoC aggressive power-saving control technology for ultra-low power consumption platforms



Toshiba has developed a control technology that realizes significant power savings by aggressively transiting the core device SoC (System on Chip) of battery-operated information devices to the power-saving mode. We tried this technology on a test model loaded with electronic paper (a type of battery-operated information device) and found that the power consumption was reduced by up to one-fifth. The details of this technology were presented at CoolChips 2014 held in Yokohama from April 14 to 17.

Development background

Battery-operated information devices such as field servers and tablet PCs for integrating sensor data in a machine-to-machine (M2M) system consume a large amount of power and so their batteries run out quickly. The SoC of these devices transits to a power-saving mode called deep sleep* when the battery is running low or the terminal is not in use (standby state), and switches to deep sleep during a long standby to conserve battery power. However, the SoC cannot transit to the deep sleep mode to save power while the device is being used.

* A state in which the CPU, all modules in the SoC including I/O driver, and external high-frequency clock are stopped.

SoC aggressive power-saving control technology

Typically, the CPUs in most information devices spend little time on processing and remain idle for most of the time until they are given work to do or instructions for processing. For example, a field server merely integrates sensor data at the interval of sensor node measurement and sends it to the cloud, and so is mostly in the standby state. Likewise, a tablet terminal is often viewed but is not being operated for most of the time. By reducing the power consumption of these CPUs in the idle state, the battery life can be extended dramatically.
This technology dramatically saves power by transiting the SoC of an operating information device to the deep sleep mode whenever possible when it is in the idle state. To enable the SoC to determine whether or not to transit to the deep sleep mode, we have developed a mechanism to determine whether the idle time is long enough to provide a power-saving effect, and to identify whether there are peripheral devices that could be adversely affected if the SoC switches to deep sleep. We also made cache memory processing faster so that the SoC can transit to and recover from deep sleep more quickly than before.
With these technologies, we succeeded in reducing power consumption while minimizing the deterioration in response performance.
We tested this technology on a test model loaded with electronic paper to measure the power consumption, and found that it reduced the power to one fifth, whereas conventional models could save only up to 50%. This means that the battery lasts three times longer when turning the page every 40 seconds.


We will continue to study technologies to develop an ultimate ultra-low power consumption platform combined with our own SoC.