Tokyo--Toshiba Corporation today announced the world's first one-chip, standalone and self-learning ATM cell multiplexer/demultiplexer that meets the ATM-Forum Universal Test & Operations PHY Interface for ATM (UTOPIA) specification. The new LSI, TC35885TB, supports multiplexing and demultiplexing of up to 31 PHY ports and is designed for application in Asynchronous Transfer Mode (ATM) switches/concentrators and DSLAM.

TC35855TB was codeveloped by the Toshiba Electronics Europe GmbH LSI design & engineering center in Duesseldolf(Germany) and Camberley(UK) , and Toshiba Corporation. It incorporates a new ATM cell multiplexer/demultiplexer designed to the UTOPIA Level 2 specification and supporting connection of several physical layer devices (8-bit mode/16-bit mode) to a single ATM layer device (16-bit mode). Each port can store up to 30 receive cells and 16 transmit cells in dedicated FIFOs. Accordingly four full duplex ATM cell streams can be multiplexed/demultiplexed into a single data stream of up to 800 megabits per second. TC35885TB operates in stand-alone mode and can handle Idle/ Unassigned/ SOC-error conditions without support of microprocessor.

The new LSI will be offered in 256-pin T-BGA package. Low-power 0.35μm CMOS process technology facilitates 3.3V operation with 5V-tolerant inputs. Samples will be available from June 1999, at 7,000 yen in Japan. Monthly production of 50,000 units is slated to start in October this year.

Key features of TC35885TB

• Full-duplex 4:1 ATM cell mux/demux
• Up to 200Mbps transfer rate at each PHY layer interface (8-bit/25MHz)
• Up to 800Mbps transfer rate at the ATM layer interface (16-bit/50MHz)
• Selectable 8/16-bit wide UTOPIA Level 2 ports on PHY side
• 16 bit wide UTOPIA Level 2 interface on ATM layer side
• Independent PHY UTOPIA clocks per port

Specifications of TC35885TB

• Process: Advanced low-power 0.3μm CMOS
• Power Supply: 3.3V
• Tolerant Inputs: plus 5V
• Frequency: 50MHz
• Package: T-BGA 256 pin
• JTAG port for boundary scan testing