| Toshiba Introduces New Generation of 16M Synchronous DRAM Line Up
22 February, 1996
The line-up consists of 6 basic chip models, configured in 24 versions differentiated by speed, bit structure and interface. Their high speed performance and multi-bit structure are suited to a wide range of uses in powerful information and communications systems, including the buffer memories of MPEG-2 decoder LSIs, a key component of multimedia equipment, and the main memory of personal computers incorporating powerful microproccessors.
The chips utilize 0.45 micron processing technology and a modified circuit structure for high speed operation, so achieving a higher speed and smaller size than the earlier generation of 16M synchronous DRAMs they replace.
Speeds range from a minimum cycle time of 8 nanoseconds at 125MHz, the fastest operating speed, to 10ns at 100MHz, 12ns at 83MHz , and 13ns at 75MHz, assuring the chips produce the high levels of performance required to support today's advanced CPUs and digital signal processors. Two interfaces are available to support high frequency operation: the conventional LVTTL (low voltage transistor transistor logic) interface, and the SSTL (stub series terminated transceiver logic) interface.
The line-up consists of three types of bit configuration: 1 megaword x 16-bit structure; 2 megaword x 8-bit structure; and 4 megaword x 4-bit structure, assuring appropriate memory configurations for a wide variety of system designs.
DRAMs are widely used as the main memories in computers, image processing equipment, and large volume data-buffer memories. With the processing speeds of CPUs incorporated in this equipment getting faster and faster, overall system performance requires DRAMs with a higher data transfer rate. Synchronous DRAMs operate synchronously with the CPU clock, promoting highly efficient cooperation between CPU and memory.
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