125MHz High Speed Data Transfer

The line-up consists of 6 basic chip models, configured in 24 versions differentiated by speed, bit structure and interface. Their high speed performance and multi-bit structure are suited to a wide range of uses in powerful information and communications systems, including the buffer memories of MPEG-2 decoder LSIs, a key component of multimedia equipment, and the main memory of personal computers incorporating powerful microproccessors.

The chips utilize 0.45 micron processing technology and a modified circuit structure for high speed operation, so achieving a higher speed and smaller size than the earlier generation of 16M synchronous DRAMs they replace.

Speeds range from a minimum cycle time of 8 nanoseconds at 125MHz, the fastest operating speed, to 10ns at 100MHz, 12ns at 83MHz , and 13ns at 75MHz, assuring the chips produce the high levels of performance required to support today's advanced CPUs and digital signal processors. Two interfaces are available to support high frequency operation: the conventional LVTTL (low voltage transistor transistor logic) interface, and the SSTL (stub series terminated transceiver logic) interface.

The line-up consists of three types of bit configuration: 1 megaword x 16-bit structure; 2 megaword x 8-bit structure; and 4 megaword x 4-bit structure, assuring appropriate memory configurations for a wide variety of system designs.
The multi-bit structure is suited to the mainstream 32/64-bit input/output bus configuration of CPU systems in PCs. Just four 2Mx8-bit chips for 32-bit CPUs or four 1Mx16-bit chips for 64-bit CPUs can construct an efficient CPU system with 8 megabytes of main memory, the capacity required for smooth operation of PCs.

DRAMs are widely used as the main memories in computers, image processing equipment, and large volume data-buffer memories. With the processing speeds of CPUs incorporated in this equipment getting faster and faster, overall system performance requires DRAMs with a higher data transfer rate. Synchronous DRAMs operate synchronously with the CPU clock, promoting highly efficient cooperation between CPU and memory.

Models

Name	Bit Structure	Minimum Cycle Time	Interface
TC59S1616AFT	1M x16-bit	8/10/12/13	LVTTL
TC59S1617AFT	1M x16-bit	8/10/12/13	SSTL
TC59S1608AFT	2M x8-bit	8/10/12/13	LVTTL
TC59S1609AFT	2M x8-bit	8/10/12/13	SSTL
TC59S1604AFT	4M x4-bit	8/10/12/13	LVTTL
TC59S1605AFT	4M x4-bit	8/10/12/13	SSTL

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Major specifications

Process	0.45 micron CMOS triple layer polysilicon, double layer aluminum wiring
Power Consumption	432mW (8ns), 324mW (10ns), 288mW (12ns), 270mW (13ns)
Voltage	3.3V +/- 0.3V
Package	400-mil 50/44-pin TSOP