Press Releases 30 August, 1995 | News

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Toshiba Introduces Multi-bit 16M DRAM Utilizing EDO
Function -- Supports High Speed CPU Operation

30 August, 1995

TOKYO -- Toshiba Corporation today announced the introduction of new mul ti-bit 16 megabit
dynamic random access memories (DRAMs) with an Extende d Data Out (EDO) function that enables
high speed data transmission. Sam ple shipment will start today at prices ranging from 8,800 yen
($105) to 10,200 yen ($120). Mass production is scheduled to start in October at a monthly
production level of 300,000 units.

The new DRAMs are targeted to match increasing speed of CPU cycle time, and thus support higher
system performance. By utilizing an EDO function , the devices achieve cycle time of 25 nanoseconds
(ns) at both 5V and 3 .3V, approximately 40 percent faster than the 40ns achieved by conventio nal
fast page mode DRAMs.

The new model line-up consists of 4 types of 2-megaword x 8-bit structur e models and 8 types of
1-megaword x 16-bit structure versions. The mult i-bit structure suits the recent mainstream 32/64- bit input/output bus configuration of CPU systems utilized in PCs. Just 4 chips of 2M x 8-bit models for
32-bit CPUs and 4 chips of 1M x16-bit models for 64-bit CPUs , can construct an efficient CPU
system with an 8 megabytes main memory, a size typical of current PCs, while the EDO function
supports high spe ed operation.

1M x 16-bit models are provided with three types of refresh modes: 1k re fresh type, 4k refresh type,
which assists the system's low power consum ption, and a self-refresh type. 2M x 8-bit models are
available with 2k refresh and self-refresh.

Models: (Differentiated by bit-structure, refresh mode, package)

TC5117805BNJ-60/70, TC51V17805BNJ-60/70, TC5117805BNT-60/70,
TC51V17805BNT-60/70, TC5118165BJ-60/70, TC5116165BJ-60/70,
TC51V18165BJ-60/70, TC51V16165BJ-60/70, TC5118165BFT-60/70,
TC51V16165BFT-60/70, TC51V18165BFT-60/70, TC51V16165BFT-60/70

Major specifications:


Process:               0.5 micron CMOS
Bit-structure:         2 megaword x 8-bit/1 megaword x 16-bit
Voltage:               5V/3.3V single power supply
Access time:           60/70 nano seconds
Cycle time under EDO:  25 nano seconds
Mode:                  EDO (Hyper page mode)
Package:               28-pin 400-mil SOJ/TSOP (2M x 8-bit types)
                       42-pin 400-mil SOJ, 44-pin 400-mil TSOP 
                                           (1M x 16-bit types)

EDO function:

Extended Data Out is an enhanced read/write operation mode differing fro m the conventional fast
page mode. It cuts the length of wait state incl uded in each read/write operating cycles, so attaining
shortening of cyc le time. Corresponding to the trend of faster CPU operating speed, the mainstream
of DRAMs is shifting from fast page mode utilization to EDO u tilization.

Information in the press releases, including product prices and specifications, content of services and contact information, is current on the date of the press announcement,but is subject to change without prior notice.