Sample shipments of the new DRAM will start today. at a price of 12,000 yen per unit. Mass production is scheduled to start in August, at a monthly production level of 100,000 units.

DRAM performance has been outpaced by progress in the micro processing units (MPUs) that control computer operations. SRAM-based cache memory, an interface between the CPU and main memory, is used to compensate for the relatively slow access times of DRAM, but this pushes up hardware costs and the overall size and complexity of computers.

The new chip uses 0.5 micrometer CMOS process technology and integrates an 18M (2M word x 9 bit) memory capacity and a Rambus interface. The RAM is composed of two independent banks of 1M byte cell arrays. Each has a 2K byte sense amplifier, which acts as a cache and allows data to be moved in and out at a rate of 500M bytes per second. On-chip registers allow the Rambus DRAMs to directly connect to MPUs and controllers and so eliminate the need for external logic ICs.

Toshiba is also developing 8M Rambus DRAMs (1M word x 8 bit) specially for graphic processing and 16M Rambus DRAMs (2M word x 8 bit). Both are expected to be available in this year.

Note: Rambus is a trademark of Rambus Corporation.

Specification

Structure:     2M word x 9 bit
Process:       0.5 micrometer CMOS, triple layer polysilicon,
               double layer aluminum wiring
Performance:   Clock cycle time:             4ns
               Burst read/write cycle time:  2ns
               Hit read time:                10 clock cycle
               Hit write time:               4 clock cycle
Package:       TC59R1809VK: 32-pin 11mm height Surface Mount
               Vertical Package (SVP)
               TC59R1809HK: 36-pin 11mm width Surface Mount
               Horizontal Package (SHP)