| Toshiba Develops 32-Megabit NAND Flash EEPROM
15 February, 1995
TOKYO -- Toshiba Corporation today announced that it has developed a 32-megabit NAND flash electrically erasable programmable read only memory (EEPROM). The new device is fabricated with 0.425 micrometer CMOS process technology and achieves a high speed access time of 28 nanoseconds with either single 3.3V or 5V power supply. The new device also offers the world's fastest data erasure operation of any EEPROM: single block erasure takes 2.5 milliseconds, while all blocks can be erased in only 5 milliseconds.
Flash memory is widely recognized as a promising alternative to disk-based storage, particularly in portable computers and personal digital assistants that require a combination of large memory capacity and portability. Toshiba has already mass-produced 16-megabit devices, and plans to start sample shipments of its new 32-megabit device this year.
The new technologies incorporated in the 32-megabit NAND flash memory will be announced tomorrow at the International Solid State Circuits Conference '95, in San Francisco, U.S.
Backgrounds of the new development:
An EEPROM is a non-volatile memory device -- a semiconductor chip that retains data even when its power supply is turned off, and which allows users to freely erase and replace data. EEPROMs offer advantages in size and weight, low power consumption and high resistance to shock, making them leading candidates for providing smaller, lighter, non- mechanical data-storage devices in place of hard disk drives. The versatility of EEPROM has already promoted significant growth in demand for the devices.
Toshiba invented flash memory, and has followed up its pioneering development work with a NAND-structure based flash memory. Toshiba believes that NAND offers a smaller memory cell and lower manufacturing costs than the NOR-structure flash memory. It also promotes efficient operation by allowing data read-out/input during data erasure, and erasure of any data block at any time.
Main features of the newly developed device:
Process technology: 0.425 micrometer CMOS technology Memory cell: Double polysilicon structure NAND memory cell Memory organization:(4M + 128K) x 8 bits Chip size: 7.14mm x 14.62mm Function: Serial Data In/Data Out Auto Page Program Auto Block Erase Auto Multi-Block Erase Suspend/Resume Status Read Reset Function control: Command control method Cycle time: 35 nanoseconds Program time: 0.4 microseconds (per byte) Access time: 28 nanoseconds (serial access time) Erase time: 2.5 milliseconds (1 block) 5.0 milliseconds (Whole chip) Supply voltage: Single 3.3V/single 5V
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