Now let's consider the next step, "sifting" (Fig. 1 - (2)).
First, the transmitter converts the photon data sent to the receiver in the previous step into an electrical signal and inputs it into the sifting process. The receiver, as well, converts the photon data received into an electrical signal and inputs it to the sifting process. The bit information selected through sifting is then passed on to the next step as data that can be used for the cryptographic key.
Here, Toshiba has developed specially-designed hardware circuits that optimize the processes involved in converting detected photons into electrical signals and sifting them. These circuits are built into both the transmitter and the receiver to process signals rapidly.
For the third step, "error correction" (Fig. 1 - (3)), we've moved to using the Low Density Parity Check (LDPC) error correction method.
This is simpler than the methods used in the past, and error correction is performed faster as the result of switching to an algorithm that supports parallel processing. The process is further accelerated by implementing LDPC using a hardware accelerator that has been improved to better handle quantum key distribution.
The last step, "privacy amplification" (Fig. 1 - (4)) involves high computational complexity and time-intensive computation. We've parallelized this computation to shorten the amount of time it takes to perform privacy amplification (*2).
By integrating the elemental technologies used in these cryptographic key generation steps, in 2017 we broke a new world record for key delivery: 13.7 Mbps (*3).