TOSHIBA REVIEW
2012 VOL.67 NO.4

  Special Reports

Lithography Technologies Supporting Evolution of Semiconductor Devices

Innovation of Advanced Lithography Technologies Driving Progress of Semiconductor Devices
SAITO Shozo

Trends in Semiconductor Lithography Technologies and Toshiba's Approach
HIGASHIKI Tatsuhiko / ONISHI Yasunobu
Lithography technology, which transfers a device circuit pattern printed on a mask to a silicon wafer using an exposure tool, plays a critical role in the semiconductor device manufacturing process and is continuously evolving to realize the shrinkage of semiconductor devices. As optical lithography, the mainstream technology, will reach the theoretical limit of resolution, a paradigm shift to next-generation lithography technologies is taking place in response to the need for further reductions in the size and cost of semiconductor devices.
Toshiba is not only developing individual element technologies, including exposure tool technologies, mask technologies, clean track technologies, optical proximity correction (OPC) technologies, and design for manufacturability (DFM) technologies, but has also been achieving world-class results in developing the total optimization of these element technologies utilizing the full spectrum of its capabilities as an integrated device manufacturer from design to production.

Lithography Design and Integration Methodologies Using Computational Science
TANAKA Satoshi / MIMOTOGI Shoji
A lithography system to fabricate microcircuit patterns of semiconductor devices incorporates a wide variety of key technologies, including a mask preparation technology, optical proximity correction (OPC) technology, exposure tools, a resist technology, and so on. Advances in such lithography technologies are essential in order to form critical circuit patterns for higher integration of semiconductor devices.
Toshiba is continuously engaged in the development of lithography design and integration techniques that realize optimal lithography performance by integrating all related engineering technologies, in order to promote and accelerate the miniaturization of semiconductor devices. We are also developing and applying a lithography simulation technique that is playing an important role in the expansion of lithography design and integration techniques and is evolving into the new field of computational lithography.

Optical Proximity Correction and Design for Manufacturability Technologies for Shrinkage of Semiconductor Devices
KOTANI Toshiya / MASHITA Hiromitsu / UNO Taiga
Optical proximity correction (OPC) and design for manufacturability (DFM) technologies are essential for the shrinkage of semiconductor devices to resolve any device patterning challenges in conjunction with design, mask, and wafer process technologies. In these technologies, cutting-edge computational patterning technology is constantly required to break through the trade-off between the improvement of patterning prediction accuracy and reduction of computational time.
Toshiba developed OPC and DFM technologies ahead of its competitors in the industry, and has been continuously achieving significant results in the advancement of both optical lithography and next-generation lithography. As a result of the development of these technologies, we developed the world's first NAND flash memory with a process on the order of 10 nm in 2011.

Advanced Mask Manufacturing Technologies
ITOH Masamitsu
Lithography technologies are applied to high-volume manufacturing of semiconductor devices using a mask to print an image of a circuit pattern. With the increasing shrinkage of mask patterns accompanying the ongoing shrinkage of semiconductor devices, technologies for the manufacturing of masks without defects are becoming essential to achieve a high yield rate in advanced semiconductor manufacturing processes.
Toshiba is promoting the innovation of mask manufacturing technologies in cooperation with the Toshiba Group and its business partners, and has established D. T. Fine Electronics Co., Ltd. (DTF) with Dai Nippon Printing Co., Ltd. in order to supply masks that serve as a key driving force for the shrinkage of semiconductor devices. We are now developing advanced mask manufacturing technologies and equipment for extreme ultraviolet (EUV) lithography that have different structures from conventional deep ultraviolet (DUV) masks.

EBM-8000 Electron Beam Mask Writer for Mask Fabrication in Manufacturing of Semiconductor Devices of 22 nm Node and Beyond
YOSHITAKE Shusuke / SAITO Masato
The mask is a vital element of lithography technology, which transfers a device circuit pattern to silicon wafers, for the high-volume manufacturing of semiconductor devices. Electron beam (EB) mask writers have long been used to fabricate masks, taking advantage of electron beams to electromagnetically control the irradiation position and feature size.
NuFlare Technology, Inc. is engaged in the development of the EBM series of EB mask writers with high accuracy and high manufacturability based on a variable-shaped beam and vector scanning technology developed by Toshiba. The EBM-8000, the latest model in the EBM series, is the world's only EB mask writer for the 22 nm half-pitch generation of devices focusing on increasing throughput and improving the dimensional and positional accuracy of patterns. The first EBM-8000 was delivered to Toshiba in 2010, and is contributing to the development and fabrication of leading-edge masks for our advanced semiconductor devices.

"ARESTM" Dry Etching Equipment for Next-Generation Mask Processing
IINO Yoshinori / YOSHIMORI Tomoaki / IWAMI Munenori
Shibaura Mechatronics Corporation, in cooperation with Toshiba, started the development of "ARESTM" (Advanced Reticule Etch System) dry etching equipment for mask processing in 2006, and began commercial production in 2009.
ARESTM, in which up to four dry etching units can be installed, is designed to deal with a number of thin dry film etchings, and is equipped with an equipment engineering system (EES) that enhances the reliability management of dry etching performance. We also developed an extreme ultraviolet (EUV) mask dry etching process in 2010, and have performed vertical pattern processing of 44 nm half-pitch resolution.

Mask Inspection Technologies for Manufacturing of Advanced Semiconductor Devices
ISOMURA Ikunao / TSUCHIYA Hideo / KIKUIRI Nobutaka
With the progressively higher integration and capacity of semiconductor devices in recent years, improvement of the performance of mask inspection technologies for reduction projection lithography has become increasingly important. Demand has been growing for the early development of a mask defect inspection system with appropriate performance for advanced device node sizes.
Toshiba has been developing mask inspection technologies since the 1980s. In cooperation with NuFlare Technology, Inc., we have now developed the NPI-7000 mask defect inspection system that can handle cutting-edge devices of less than 20 nm half-pitch node with almost double the throughput compared with conventional systems. The NPI-7000 is also equipped with a mask inspection function for extreme ultraviolet (EUV)lithography for the first time in the world, and is playing a role in the advancement of our semiconductor manufacturing technologies in parallel with the development of lithography technologies.

"EBeyeM" EUV Mask Inspection Tool for EUV Lithography Applying Projection Electron Microscope Technology
YAMAGUCHI Shinji / NAKA Masato / HIRANO Takashi
Attention is being increasingly focused on the research and development of mask inspection technologies to detect small defects of less than 20 nm in size on a mask, as one of the shrinkage technologies supporting the future manufacturing of semiconductor devices.
Toshiba, in cooperation with Ebara Corporation, has developed the "EBeyeM" extreme ultraviolet (EUV) mask inspection tool for EUV lithography equipped with a projection electron microscope (PEM) for the first time in the industry. We have confirmed that, unlike conventional electron beam inspection tools that require a long inspection time as a trade-off for high resolution, the newly developed electron beam inspection tool can detect small defects of less than 20 nm in size on a mask with almost the same inspection time as that required for optical inspection tools.

Extreme Ultraviolet Lithography Technologies Realizing Semiconductor Device Pattern Shrinkage
KYOH Suigen / INOUE Soichi
Extreme ultraviolet (EUV) lithography holds promise as a means of promoting the further shrinkage of semiconductor devices. The wavelength of 13.5 nm used by EUV lithography, which is less than one-tenth that used by conventional lithography technologies, leads to extremely high resolution allowing 22 nm half-pitch patterns to be resolved, but still has remaining technological issues.
In order to overcome such challenges, Toshiba has been contributing to efforts to accelerate the development of EUV lithography technologies for high-volume manufacturing by participating in the EUV consortium and alliance. As a result, we have developed an EUV exposure system equipped with a reflective mirror that can expose the same area as conventional systems, high-resolution resists of 15 nm half-pitch modulation, and a mask inspection system to detect mask phase defects, and have confirmed the effectiveness of these new technologies. Experiments on prototype dies of 28 nm half-pitch pattern manufactured by this system have verified that its performance is sufficient for practical application to high-volume manufacturing.

UV Nanoimprint Lithography Technology
NAKASUGI Tetsuro / KONO Takuya / YONEDA Ikuo
Demand for reduction of the feature sizes and manufacturing costs of semiconductor devices has been increasing in recent years. Ultraviolet (UV) nanoimprint lithography technology has been attracting considerable attention as a candidate next-generation lithography technology to solve these issues.
Toshiba is engaged in research targeted at the application of UV nanoimprint lithography technology to semiconductor devices. We have confirmed that UV nanoimprint lithography technology can form high-quality resist patterns with a resolution exceeding 20 nm and a line-edge roughness of about 2 nm, while achieving an overlay accuracy exceeding 15 nm (average +3σ). This technology has the potential to become a future solution for the manufacturing of semiconductor devices such as flexible devices, by overcoming the trade-off between the reduction of defects and improvement of throughput.

Directed Self-Assembly Lithography Technology
KIHARA Naoko
In recent years, attention has been focused on self-organizing technology as one of the next-generation lithography technologies, because of its ability to form regular nanometer-scale patterns by the application of self-organized diblock copolymers. However, as the self-organizing phenomenon is a physical process, it is necessary to control the alignment of self-assembled patterns for the fabrication of actual circuit patterns of semiconductor devices.
Toshiba has been developing a directed self-assembly (DSA) process that is considered to have the potential to realize sub-10 nm feature size devices using a method combining the photolithographic process and a self-organizing material.

   

  Feature Articles

Water-Lubricated Plastic Bearing for Hydroelectric Power Systems
THAN TRONG Long / OGUMA Tadashi / KIZAKI Yasumi
In order to prevent lubricant oils of oil-lubricated white metal bearings for hydroelectric power systems from leaking into rivers, demand has been increasing for water-lubricated bearings in recent years.
To meet this market demand, Toshiba has developed a water-lubricated plastic bearing fabricated by adding carbon fiber and potassium titanate whisker (Cf-KTiOw) to polytetrafluoroethylene (PTFE) to remarkably improve wear and seizure resistance. The characteristics and reliability of the PTFE-based composite bearing have been confirmed through demonstration tests including performance tests, endurance tests, and start/stop operation tests using experimental apparatus operated under conditions equivalent to those of a hydroelectric power plant. We are planning to expand the use of this PTFE-based composite to other industrial applications for energy saving and reduction of environmental burdens.

Data Analysis Technology Focusing on Operational Risk Management
HAYAKAWA Rumi / EGAWA Seiji / ODAKA Satoshi
Toshiba Solutions Corporation has been engaged in research and development of data analysis technologies to extract useful information and knowledge for business activities from large volumes of different data in companies.
We have now developed a data analysis technology for application to the management of operational risk in financial institutions. This technology can quantitatively show the conditions of occurrence of mistakes in office work by analyzing the correlation between the volume of tasks and number of mistakes from actual data, and can identify the characteristics of each organization in the company by cross-checking and evaluating the data of multiple organizations. We have been participating in a data analysis consortium for financial institutions established in May 2011, and will offer the results obtained by this data analysis technology to the consortium aiming at both the promotion of information sharing among users and the improvement of their office work.

   

  Frontiers of  Research & Development

Nanocarbon Interconnects Overcoming Limitation of Metal Interconnects
"Auto Clean" Noise Reduction Technology for Televisions in Emerging Markets