|
Semiconductor Nonvolatile Memories Past, Present, and Future of Semiconductor Nonvolatile Memories MOMODOMI Masaki Trends in Semiconductor Nonvolatile Memories and Toshiba's Approach OHSHIMA Shigeo Large-capacity nonvolatile memories, as typified by NAND flash memories, have been expanding the market for external storage devices for mobile products, and are utilized in all areas of people's daily lives. Toshiba's memory business has been achieving successful growth, and we have consistently realized innovations in various leading-edge technologies as the inventor of flash memory. Although the challenges over the physical scaling limit will become steep, we are aiming to overcome such issues by making use of our long-accumulated experience and record of innovations. We are also engaged in research and development for future technology breakthroughs, including innovative post-NAND nonvolatile memories, thereby maintaining our technical leadership in the world storage market. Technologies Supporting Evolution of SSDs TSUCHIYA Kenji Notebook PCs equipped with solid-state drives (SSDs), featuring shock and vibration durability due to the lack of moving parts, appeared on the market around 2006. However, single-level-cell (SLC) NAND flash memories were used in SSDs at that time, and it was believed that multilevel-cell (MLC) flash memories, while they could double the storage capacity compared with SLCs, were not applicable because of a lack of reliability. In 2008, Toshiba developed the world's first SSD equipped with MLC NAND flash memories and realizing a low write application factor (WAF), thereby increasing the reliability of MLC SSDs. This was achieved through the analysis of actual PC users' workload in detail, as well as the development of a new NAND cache system and an appropriate NAND management algorithm. MLC NAND flash memories have now become the mainstream for SSDs used in notebook PCs, and are contributing to new values such as a thin and small form factor (SFF), very low standby current, and instant-on capability. Design Technology for 64 Gbit 2-Bit Multilevel-Cell NAND Flash Memory Using 24 nm Process FUKUDA Koichi / SATO Junpei / EDAHIRO Toshiaki The memory density (capacity per mm2) of NAND flash memories has been increasing by around 30% annually accompanying the scaling of memory cells. However, as the pace of scaling is showing a tendency to slow down because of the difficulties involved, there is a growing need for reduction of the peripheral area other than the memory cell array. Toshiba has developed a 64 Gbit 2-bit multilevel-cell (MLC) NAND flash memory that achieves a memory density of 54 Mbytes/mm2, together with both a high effective cell area of 79% and a small die size of 151 mm2, using 24 nm complementary metal-oxide semiconductor (CMOS) technology. BiCS Flash Memory for Realization of Ultrahigh-Density Nonvolatile Storage Devices AOCHI Hideaki / KATSUMATA Ryota / FUKUZUMI Yoshiaki Ultrahigh-density memory technologies to realize a three-dimensional (3D) memory cell array have been attracting considerable interest as a solution to deal with the continuous increase in bit density and reduction of bit cost expected in the future. Applying its proprietary technologies, Toshiba has developed the world's first bit-cost scalable (BiCS) flash memory technology to achieve a 3D memory cell array with an extremely low fabrication cost. Using new array structures and technologies to improve the characteristics of the memory device, we fabricated a prototype 32 Gbit BiCS flash memory test array with a 16-layer memory cell using a 60 nm design rule, and verified its multilevel functionality. Spin-Transfer Torque Writing MRAM with Perpendicular Magnetic Tunnel Junction Devices YODA Hiroaki Field writing magnetoresistive random access memories (MRAMs) have been actively developed as nonvolatile working memories because of their attributes including unlimited endurance and fast read/write speed, exceeding those of other nonvolatile memories. However, field writing MRAMs lack scalability due to their inefficient writing. In response to this situation, intensive efforts have been focused on spin-transfer torque writing MRAMs in recent years. Toshiba has developed a magnetic tunnel junction device with perpendicular anisotropy (abbreviated as P-MTJ device) for storage devices to extend scalability. Since we demonstrated the world's first spin-transfer writing on P-MTJ devices in 2007, we have achieved small-current writing of several tens of microamperes and a large magnetoresistance (MR) of more than 200%. We are now engaged in research and development of practical applications for the realization of a large-capacity gigabit-class memory. Erase and Program Conditions Affecting Retention Lifetime of NAND Flash Memories MATSUKAWA Naohiro The data retention lifetime of NAND flash memories is significantly affected by the erase and program cycling conditions including the interval and temperature, even when the number of times of cycling is the same. Therefore, data retention lifetimes corresponding to each application have to be estimated under various operating conditions. In order to estimate the data retention time more accurately, it is necessary to measure the decrease in the threshold voltage (Vth) of the memory cell responsible for data retention failure determined by two parameters; namely, the rate of change with time and time offset of Vth. Toshiba has developed a model through experiments that explains the dependence of the erase and program cycling conditions on the two parameters for each generation of NAND flash memory, and provides our products with confirmed data retention lifetimes for each application. Packaging Technologies Supporting High-Capacity Semiconductor Memories OMORI Jun The demand for high-density memories has been increasing as a result of the reduction in market prices of NAND flash memories and the shift from image data to moving-picture data in recent years. The emergence of mobile devices such as solid-state drives (SSDs), smartphones, and tablet PCs has also been a strong driver of this trend. In addition, high robustness against drop impact and temperature variation for packages offering high board-level reliability is required. To meet these requirements, Toshiba has been developing memory packaging and assembly technologies including high-capacity packaging technologies and multi-die stacking technologies for thin packages. We are also promoting quality improvement activities to design robust packages that are guaranteed in accordance with board-level reliability using simulation technologies. |