| Semiconductor Process Technologies Toward the Fusion of New Materials and New Process Technologies into the Deep-Submicron Semiconductor Process
HIRAKI Shunichi Recent Progress of Semiconductor Process Technologies and Future Challenges
SUGIMOTO Shigeki / KAMIGAKI Tetsuya / KAMIJO Hiroyuki
Semiconductor process technologies are making rapid progress in terms of scale, performance, and cost to meet customers' requirements. Nanofabrication and the use of exotic materials are two major pillars of semiconductor process development. Nanofabrication is being achieved as a result of continual technological innovation, enabling interconnection size to be reduced by about 85 % annually. At the same time, exotic materials are constantly being researched to meet the demand for higher device performance. Toshiba has the world's top-level capability of these process technologies that encompass many different fields, and has succeeded in developing new-generation semiconductor devices at the leading edge of the technology roadmap. Challenges and Innovations in Advanced Lithography Technology
MORI Ichiro / HIGASHIKI Tatsuhiko
Large-scale integration of semiconductor devices offers such advantages as higher performance, enhanced functions, and greater reliability as well as reduced production cost. To achieve large-scale integration on a practical basis, there is a strong need for progress in ultrafine processing technology, which forms the critical circuit patterns. A lithography system to fabricate microcircuit patterns of semiconductors incorporates a number of key technologies; namely, mask making, optical proximity correction (OPC), exposure tools, resist technology, and metrology. To promote semiconductor miniaturization, Toshiba is developing a lithography designing technique that realizes optimally effective lithography by integrating all related engineering technologies. High Performance Transistor Technologies
SUGURO Kyoichi / EGUCHI Kazuhiro
Reduction of both the gate insulator thickness and source/drain depth is very important in high-performance transistors. Since the gate oxide thickness decreases to below 1 nm in the next technology node, the gate leakage current becomes unacceptably large for transistors. Toshiba has succeeded in increasing the physical thickness and reducing the gate leakage current by using hafnium silicate (HfSiON), which has a dielectric constant three times larger than that of silicon dioxide (SiO2). In order to eliminate the gate depletion of 0.2-0.5 nm in equivalent oxide thickness, dual-work-function metal gates were developed. On the other hand, the pn junction depth is required to be less than 20 nm in the source/drain extension region. We have therefore developed an ultra-low-energy ion implantation technology and a technology for ultra-rapid thermal annealing in as short as 1 msec. To reduce pn junction leakage in the contact region, we have also developed a nickel silicide (NiSi) technology that achieves a silicon erosion thickness of less than 20 nm. These technologies dramatically improve transistor performance. Advanced BEOL Technology
YODA Takashi / HASUNUMA Masahiko / MIYAJIMA Hideshi
In recent years, great progress has been achieved in back end of line (BEOL) process development since the advent of the 130 nm technology node. This progress includes changing the wiring material from Al to Cu, and the dielectric material from the traditional silicon dioxide (SiO2) to low-dielectric-constant (low-k) materials. Moreover, a high-performance BEOL process requires a porous material. However, porous low-k material degrades the mechanical strength of the film and the interfacial adhesion of films. To meet the above requirement, Toshiba has developed the leading-edge technology in the Cu/low-k BEOL process. This advanced BEOL process technology centers around the stacked dielectric structure, the reactive ion etching (RIE) process, and improvement of the mechanical strength of the film. Reactive Ion Etching
OHIWA Tokuhisa
Reactive Ion Etching (RIE), which enables employment of thin resist mask, is an indispensable technology for manufacturing large-scale integrated circuits (LSIs) from the 90 nm node onward. Toshiba has developed a spun-on-carbon film with minimum impurities for etching masks. Using a stacked mask process (S-MAP), which uses a layered mask consisting of a thin film resist, spin-on-glass (SOG), and the newly developed carbon film, we have made possible a micro-processing technology using thin film resists. The new technology realizes the etching of high-aspect-ratio holes, which require high selectivity to etching masks. We have also developed a 100 MHz and 3.2 MHz radio frequency (rf) power superimposed RIE technology, which is called dual- frequency superimposed RIE (DFS RIE), which makes precise ion energy control possible. DFS RIE realized selective etching of low-dielectric-constant (low-k) SiOC film, which is a key material for high speed LSIs, to Si3N4 mask. High-Density Packaging Technologies
HARADA Susumu / SUGIZAKI Yoshiaki / TAKUBO Chiaki
Accompanying the rapid progress of the digital network information society, there is strong demand for high functionality and miniaturization of mobile personal digital assistants (PDAs). At the same time, ultrahigh-speed operation is required for a high-performance server to process large volumes of communicated information. Toshiba has developed a three-dimensional stacking technology for chips and packages for mobile PDAs. We have also developed a flip-chip package technology with good electrical and thermal properties for use in high-performance servers. Discrete Device Manufacturing Process Technology
SHIMADA Kizashi / SUGIYAMA Hitoshi / YOSHITAKE Shunji
Toshiba has developed a low-noise amplifier (LNA) featuring the world's lowest noise figure, incorporating a silicon-germanium heterojunction bipolar transistor (SiGe-HBT) and high-output-power laser diode (LD), for application to 12x DVD recorders. The key points of the lower noise figure of the SiGe-HBT are decreases in the base resistance and in the capacitance between the base and the collector. These were attained by optimization of the base doping profile and the adoption of a 0.18 µm emitter using low-cost i-line lithographic technology. The high light output power of the LD, whose key points are linearity of the current vs. optical output characteristics, catastrophic optical damage (COD) tolerance, and improved heat radiation, was realized by fine ridge patterning with reactive ion etching (RIE), charge control techniques on the insulator-semiconductor interface, and optimization of the cavity length. |
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